4 PIC18 Forth

The Microchip PIC18 microcontroller architecture with 8-bit data word size and 16-bit instruction word size maps quite straightforwardly to a stack machine, making it an ideal primary architecture for Staapl. The implementation in Staapl uses the WREG register to implement the top of stack register, and INDF0 to point to the rest of the parameter stack in SRAM. Most arithmetic and conditional jump instructions are used to implement basic forth data and control operations in a fairly optimal way. The compiler produces native code, eliminating the need for an on-target interpreter. Forth code can be used in interrupt routines without trouble. The PIC18 language includes a full RPN assembler. The PIC18F stores code in Flash ROM memory, but has the ability to program itself. This is used to provide run-time code upload in the interaction mode.